This invention relates generally to electro-static discharge transistors connected to circuit input/output pads and used to protect semiconductor devices from damage resulting from electrostatic discharge.
Electrostatic discharge (ESD) can be a source of destruction for semiconductor devices. Various input protection circuits may be used to protect the input circuits from electrostatic discharge damage. However, these same protection circuits are generally not used for output buffers and input/output (I/O) pads due to performance constraints. See for Example, Y. Wei, Y. Loh, C. Wang and C. Hu, MOSFET Drain Engineering for ESD Performance, EOS/ESD Symposium, 1992, pp. 143-148. For output buffers and I/O buffers, n-channel pull-down transistors must be properly designed to ensure adequate ESD performance. These n-channel pull-down transistors used for I/O buffers, n-channel pull-down transistors are sometimes referred to as ESD transistors.
As technology scales, various processing changes are made which can effect the ability of ESD transistors to function optimally. For example, in CMOS technology, as circuitry has decreased in size, placing a metal-silicide region immediately over the source-drain region of transistors has been used to minimize the series source-drain resistance. See for example, Silicon processing for the VLSI Era ----Volume 2, Process Integration, pp. 144-152. However, placing metal-silicide regions above source-drain regions of ESD transistors can seriously degrade ESD hardness, increasing the possibility of ESD damage to circuitry within semiconductor devices. See for example, C. Duvvury, R. N. Rountree, Y. Fong, and R. A. McPhee, ESD Phenomena and Protection Issues in CMOS Output BuffersIEEE/IRPS, 1987, pp. 174-180.